1. Field of the Invention
The present invention generally relates to a semiconductor device such as a large-scale integration (LSI) circuit. More specifically, the present invention is directed to a technique capable of stabilizing operation characteristics of such a semiconductor device having an element isolating film on a major surface of a semiconductor substrate.
2. Description of the Conventional Art
SRAMs (static random access memories) are volatile semiconductor devices in which memory cells are arranged at cross points between complementary type data lines (bit lines) and word lines. These data and word lines are arranged in a matrix form.
A memory cell is arranged by a flip-flop circuit and two sets of access transistors. This flip-flop circuit constitutes two storage nodes which are cross-coupled to each other. The storage nodes own bi-stable states of either (High, Low) or (Low, High), and continuously hold the bi-stable states as long as a preselected power source voltage is applied.
In this case, as to the access transistors, one semiconductor region is connected to the storage nodes (input/output terminals of the flip-flop circuit), and the other semiconductor region is connected to the complementary type data line (bit line). The gate electrodes of the access transistors are connected to the word line, and then conductive/non-conductive states of the access transistors are controlled by way of this word line.
When data is written, the word line is selected so as to cause the access transistors to become conductive, and voltage are forcibly applied to a pair of bit lines in response to a desirable logic value, so that the bi-stable state of the flip-flop circuit is set to either (High, Low) or (Low, High).
When data is read, the access transistors are brought into conductive states, and a potential at the storage node is transferred to the bit line. Now, the above-described flip-flop circuit is arranged by two driver transistors and two load elements. As to this driver transistor, a drain region thereof is connected to the semiconductor region of one access transistor, and a source region thereof is connected to a ground line (VEE line). A gate electrode of the driver transistor is connected to the semiconductor region of the other access transistor. Furthermore, one of these load elements is connected to the semiconductor regions of the access transistors, and the other of the load elements is connected to a power source line (VCC line).
Very recently, the following problems are apparently brought up in SRAMs.
First, in order to reduce manufacturing cost by increasing integration degrees of SRAMS, sizes of transistors, in particular, sizes of MOS transistors are necessarily required to be reduced. However, when a gate width of an access transistor is made excessively narrow, a Vth (threshold voltage value) of the access transistor would be increased due to the narrow channel effect, so that reading operation of a memory cell is brought into an unstable condition. Therefore, it is practically difficult that the gate width of the access transistor is shortened up to the region where the Vth increase caused by the narrow channel effect happens to occur. As a consequence, as the gate width of the access transistor, such a narrowest gate width has been employed by which the Vth (threshold voltage value) increase caused by the narrow channel effect can be suppressed, so that the layout area could be reduced.
On the other hand, in order to achieve stable conditions of SRAMs, a cell ratio must be maintained higher than a preselected value (for instance, approximately 3). The cell ratio is defined by a ratio of a current value (driveability) of a driver transistor to a current value (driveability) of an access transistor. However, as previously described, if the current of the access transistor, the gate width of which has been determined, is slightly increased, then this cell ratio would be lowered, resulting in an occurrence of faulty operation.
Now, a first description will be made of the above-described failure operation due to the decrease of the cell ratio.
In general, as is known in the art, the cell operation can be stabilized by increasing a conductance ratio (current ratio) of a driver transistor to an access transistor, so-called as a xe2x80x9ccell ratioxe2x80x9d, to thereby increase a gain of an inverter, namely to make a sharp inclination of a transition portion of an inverter output. This known idea will now be described based upon an input/output transfer characteristic of one pair of inverters cross-coupled to each other, as indicated in FIG. 31.
FIG. 32 represents the input/output transfer characteristic of one pair of cross-coupled inverters. In this transfer characteristic, in order to function as a flip-flop, the inverters must own two stable points such as S1 and S2, as represented in FIG. 32. In order that a memory cell can be practically utilized, it is so designed that regions surrounded by curves shown in FIG. 32 must be made sufficiently large. As an index, a diameter of a circle indicated in this drawing is sometimes used, which is referred to as an SNM (static noise margin).
Now, a further detailed description will be made of a transfer characteristic of a memory cell of an SRAM as indicated in an equivalent circuit of FIG. 33.
Normally, since access transistors are under non-conductive states during standby, inverters of the memory cell are constituted by driver transistors and load elements. In this case, since the load elements own high impedances, an inclination of a transition portion of an inverter output becomes sharp as shown in a memory cell transfer characteristic diagram of standby in FIG. 34. An SNM becomes large. As a result, data can be held under stable condition.
On the other hand, when data is read from the memory cell, the access transistors become conductive, so that a column current flows into a storage node on a Low side. In other words, this is equivalent to such a connection that a load made of the access transistor having the low impedance is connected in parallel to the load element. The inverters of the memory cell must be handled as NMOS type enhancement node inverters constituted by driver transistors and this access transistor as the load. When the cell ratio is low, as indicated in FIG. 35, i.e., a memory cell transfer characteristic diagram during data read operation, the gain of the inverter is considerably lowered, as compared with that during standby. Namely, the inclination of the transition portion of the inverter output becomes loose.
Also, a potential at a storage node on a High side is lowered from the power source voltage level during standby up to such a potential value defined by subtracting Vth of the access transistor from the power source voltage, and the SNM is considerably lowered for the time being. At this time, if a sufficiently large SNM is not established, then the bi-stable states will be lost. There is a risk that data may be electrically destroyed.
Under such a reason, normally, the cell ratio is made large in order to avoid the above-explained data destroy. As a result, as illustrated in FIG. 36, namely a memory cell transfer characteristic when data is read in case of a large cell ratio, the gain of the inverter becomes large. In other words, the inclination of the transition portion of the inverter output becomes sharp, and the SNM is enlarged.
However, in connection with higher integration of recent semiconductor elements, since layout areas should be reduced, it is practically difficult to widen sizes (gate widths) of driver transistors. As a consequence, in order to stabilize operations of SRAMs, currents of access transistors are required to be reduced.
Referring now to FIG. 37A to FIG. 43, a description will be made of one modification similar to the conventional semiconductor device manufacturing method as described in IEEE TRANSACTIONS ON ELECTRON DEVICES VOL. 42, No. 7, July 1995, on pages 1303 to 1312.
In this case, FIG. 37A to FIG. 42B are plan views and sectional views taken along lines Bxe2x80x94B in the plan views, for schematically showing a major portion of a single SRAM cell manufactured in accordance with the conventional semiconductor device manufacturing method in a manufacturing step order. FIG. 43 is a sectional view taken along a line A1-A2 of the SRAM cell shown in FIG. 42A.
First, as indicated in FIG. 37A and FIG. 37B, a field insulating film 2 functioning as an element isolating film made of SiO2 having a thickness of approximately 3000 xc3x85 is formed on an Nxe2x88x92type silicon substrate 1 corresponding to a semiconductor substrate by employing the selective thermal oxidation method (for instance, local oxidation of silicon: LOCOS). In this selective thermal oxidation method, for example, while a silicon oxide (SiO2) film is used as a pad film, a silicon nitride (Si3N4) film deposited on this pad film is used as an anti-oxidation mask.
Thereafter, both the pad SiO2 film and the Si3N4 film are removed which are employed as the above-described selective thermal oxidation, so that an element forming region 3 is exposed from a surface of the Nxe2x88x92type silicon substrate 1.
Then, for example, a P type impurity such as boron (B) is implanted into the entire major surface of the Nxe2x88x92type silicon substrate 1 under such a condition that the implanting voltages are selected from 200 KeV to 700 KeV, and the dose amount is selected to be on the order of 1.0xc3x971012 cmxe2x88x922 to 1.0xc3x971013 cmxe2x88x922. Furthermore, the P type impurity such as boron (B) is implanted into the resultant major surface of the silicon substrate 1 under conditions of, for instance, 30 to 70 KeV and approximately 1.0xc3x971012 to 2.0xc3x971013 cmxe2x88x922, to thereby set the threshold voltages xe2x80x9cVthxe2x80x9d of access transistors T1, T2 and driver transistors T3, T4. A Pxe2x88x92type well region 4 (see FIG. 43) formed in this manner contains impurity concentration of on the order of approximately 1016 to 1018 cmxe2x88x923.
Then, a gate insulating film 5 (see FIG. 43) made of SiO2 having a thickness of, for example, 70 xc3x85 is formed on the entire surface by way of, for example, the thermal oxidation. With employment of the LPCVD (low pressure chemical vapor deposition) method, gas such as phosphine (PHs) is mixed, so that a phosphorus doped polycrystal silicon film having a thickness of approximately 10000 xc3x85 is deposited with phosphorus density of approximately 1.0 to 8.0xc3x971020 cmxe2x88x923.
Then, the photoresist is patterned into a predetermined shape by employing the photolithography, and while using this patterned photoresist as a mask, for instance, the reactive ion etching (RIE) method is applied so as to pattern the above-described phosphorus doped polycrystal silicon film, so that word lines 6a, 6d corresponding to gate electrodes of access transistors T1, T2, and gate electrodes 6b, 6c of driver transistors T3, T4 are formed.
It should be noted that although the word lines 6a, 6d and the gate electrodes 6b, 6c of the driver transistors are formed only by the phosphorus doped polycrystal silicon film in this example, these components may be made by employing, for instance, a so-called polysilicide wiring pattern made of a metal silicide such as a tungsten silicide (WSi2) film, and the phosphorus doped polycrystal silicon film.
Thereafter, for instance, arsenic (As) is implanted into the entire surface over the gate insulating film 5 while rotating a wafer under such a condition that the dosing energy is selected to be approximately 30 to 70 KeV, the implanting angle is 45 degrees, and the dose amount is selected from approximately 1.0 to 5.0xc3x97103 cmxe2x88x922 and thus Nxe2x88x92type source to drain regions 71 to 75 are formed in a region other than such regions shielded by the word lines 6a, 6d of the element forming region 3 and the gate electrodes 6b, 6c of the driver transistors. In this case, the Nxe2x88x92type source/drain regions 71 to 75 contain impurity density of on the order of 1017 to 1019 cmxe2x88x923.
Next, as indicated in FIG. 38A and FIG. 38B, an SiO2 film 9 having a thickness of approximately 500 to 1500 xc3x85 is deposited on the entire surface by employing the LPCVD method, and side wall oxide films 91 to 96 having a thickness of approximately 500 to 1500 xc3x85 are formed on side walls of the word lines 6a, 6b and also of gate electrodes 6b, 6c of the driver transistors by using the RIE method.
At the same time, in this case, the field insulating film 2 is also planed by the RIE method, so that the area of the element forming region 3 exposed from the surface of the semiconductor substrate 1 is increased. It should be noted that a dot and dash line of FIG. 38A indicates the element forming region 3 which has not yet been planed by the RIE method, and a solid line thereof indicates the element forming region 3 which has been planed.
Next, while using these side wall oxide films 91 to 96 as a mask, for instance, arsenic (As) is implanted at 50 KeV with the dose amount of approximately 1.0 to 5.0xc3x971015 cmxe2x88x922 to form N+type source/drain regions 111 to 115. At this case, for example, either arsenic (As) or phosphorus (P) may be additionally implanted at approximately 30 to 70 KeV at an implanting angle of 45 degrees into the overall surface with the dose amount of approximately 1.0 to 5xc3x9710 13 cmxe2x88x922, while rotating the wafer.
In this case, the N+type source/drain regions 111 to 115 contain impurity concentration of on the order of 1020 to 1021 cmxe2x88x923, and forms a so-called xe2x80x9cLDD (lightly doped drain)xe2x80x9d structure for relaxing an electric field near the drain by the Nxe2x88x92type source/drain regions 71 to 75 and the N+type source/drain regions 111 to 115.
In FIG. 38A, in order to clearly indicate the positional relationship among the Nxe2x88x92type source/drain regions 71 to 75, the N+type source/drain regions 111 to 115, and the side wall oxide films 91 to 96, outer edges of the side wall oxide films 91 to 96 are indicated by a dotted line and also underlayers thereof are indicated.
Next, as shown in FIG. 39A and FIG. 39B, after an SiO2 film 14 having a thickness of approximately 1500 xc3x85 has been deposited on the entire surface by using the LPCVD method, the photoresist is patterned to have a preselected form by using the photolithography technique. While using this patterned photoresist as a mask, for instance, the RIE method is applied to selectively remove the SiO2 film 14, so that such a contact hole 12 is formed in such a manner that a portion of the N+type source/drain region 113 is exposed.
Then, after a phosphorus doped polycrystal silicon film having a thickness of approximately 10000 xc3x85 and phosphorus concentration of on the order of 1.0 to 8.0xc3x971020 cmxe2x88x923 has been deposited by using the LPCVD method, a metal silicide film such as a tungsten silicide (WSi2) film having a thickness of 1000 xc3x85 is further and continuously deposited.
Then, the photoresist is patterned to have a predetermined shape by employing the photolithography technique, and while using this patterned photoresist as a mask, for example, the RIE method is applied so as to continuously pattern the above-described tungsten silicide (WSi2) film and phosphorus doped polycrystal silicon film, so that a ground wiring line 13 is formed. In FIG. 39A, in order to clearly indicate a positional relationship between the ground wiring line 13 and the gate electrodes 6b, 6c of the driver transistors, the indication of the SiO2 film 14 is omitted. Instead, an under layer of this film is indicated.
Thereafter, as shown in FIG. 40A and FIG. 40B, after SiO2 films 15 having thicknesses of approximately 1500 xc3x85 are deposited on the overall surface by using the LPCVD method, the photoresist is patterned to have a predetermined shape by using the photolithography technique. While using this patterned photoresist as a mask, for example, the RIE method is applied to selectively remove the SiO2 film 15, so that contact holes 141 to 144 are formed in such a manner that the contact holes are opened in an impurity region 112 between the access transistor T1 and the driver transistor T3, and another impurity region 114 between-the gate electrodes 6c, 6b of the driver transistors, the access transistor T2, and the driver transistor T4.
Then, a phosphorus doped polycrystal silicon film having a thickness of approximately 1000 xc3x85 and phosphorus concentration of on the order of 1.0 to 8.0xc3x971020 cmxe2x88x923 is deposited by using the LPCVD method. Thereafter, the photoresist is patterned to have a predetermined shape by using the photolithography technique, and while using this patterned photoresist as a mask, for example, the etching process is carried out by way of the RIE method. Accordingly, the above-described phosphorus doped polycrystal silicon film is patterned to thereby form connections 151 and 152.
It should be noted that in FIG. 40A, in order to clearly indicate a positional relationship between the connection lines 151, 152 and the gate electrodes 6b, 6c of the driver transistors and also the impurity regions 112, 114, the indications of the SiO2 films 14, 15 are omitted. Instead, under layers of these films are indicated.
Thereafter, as shown in FIG. 41A and FIG. 41B, after xe2x80x9cSiO2 film 16 having a thickness of approximately 100 to 1500 xc3x85 is deposited on the overall surface by using the LPCVD method, the photoresist is patterned to have a predetermined shape by using the photolithography technique. While using this patterned photoresist as a mask, for example, the RIE method is applied to selectively remove the SiO2 film 16 so that contact holes 161 and 162 are formed in such a manner that portions of the phosphorus doped polycrystal silicon films 151 and 152 are exposed.
Then, a polycrystal silicon film having a thickness of approximately 200 to 1000 xc3x85 is deposited by using the LPCVD method. Subsequently, phosphorus (p) is implanted with the dose amount of 1.0xc3x971012 to 1.0xc3x971014 cmxe2x88x922 at 30 KeV. Then, the photoresist is patterned to have a predetermined shape by using the photolithography technique, and while using this patterned photoresist as a mask, for example, the RIE method is applied. Accordingly, the above-described polycrystal silicon film is patterned to thereby form an electrode 17.
Thereafter, furthermore, the photoresist for shielding desirable positions 172 and 175 on the electrode 17 is patterned by using the photolithography technique. While using this patterned photoresist as a mask, for example, BF2 is implanted at 20 KeV in the dose amount of approximately 1.0xc3x971014 to 1.0xc3x971015 cmxe2x88x922, and the above-described photoresist is removed. Then, the resultant substrate is annealed for 30 minutes at the temperature of, e.g., 750xc2x0 C. to 850xc2x0 C. so as to activate the impurities, so that source regions 173, 176, drain regions 171, 174, and channel regions 172, 175 of P channel type TFTs (thin-film transistors) are fabricated, respectively.
It should also be noted that in FIG. 41A, in order to clearly indicate a positional relationship between the electrode 17 and the connection lines 151, 152, the indications of the SiO2 films 14, 15, 16 are omitted. Instead, under layers of these films are indicated.
Next, thereafter, as illustrated in FIG. 42a, FIG. 42B, and FIG. 13, after an interlayer insulating film 18 is formed on the electrode 17 and the SiO2 film 16, bit-line contact holes 181 and 182 opened in the impurity regions 111 and 115 are formed. Bit lines 191 and 192 made of aluminum wiring lines and being electrically connected via the bit-line contact holes 181 and 182 to the impurity regions 111 and 115 are formed, so that the semiconductor device is obtained.
It should also be noted that in FIG. 42A, in order to clarify a positional relationship between the bit lines 191, 192 and the electric elements (gate electrodes 6a, 6d of access transistors etc.) located under layers thereof, the indications of the SiO2 films 14, 15, 16, 18 are omitted. Instead, indications of under layers thereof are made.
In the above-described conventional semiconductor device, there is no problem in such a case that the bird""s beak of the element isolation oxide film is considerably small, as compared with the gate widths of the access transistors. When the minimum designed dimension of the electric elements for constituting this semiconductor device becomes smaller than, or equal to 0.5 xcexcm, the retreat of bird""s beak caused by the over etching process while the side walls are formed so as to form the LDD structure of the MOS transistor may give not negligible adverse influences to the stable operations of this semiconductor device.
As indicated in FIG. 38A, concretely speaking, the retreat of bird""s beak located near the gate electrodes 6a to 6d, which is caused by the etching process while forming the side walls 91 to 96 may cause the following problems. That is, the widths of the diffusion regions of the access transistors T1 and T4 are increased near the gate electrodes 6a and 6d, so that the stray resistance is lowered, and increasing of the currents of the access transistors T1 and T4 is induced, and eventually, the cell ratio is lowered, which may impede improvements in the reading characteristic of the memory cell.
In addition, for example, as shown in FIG. 43, in the conventional semiconductor device, there is another problem that flatness under the wiring layer such as the bit line 191 is not under good condition, and therefore this wiring layer cannot be easily patterned.
The unnecessary remove of the element isolating film such as retreating of the bird""s beak occurred during the manufacture of the conventional semiconductor device will impede improvements in the stable operations of this semiconductor device.
The present invention has been made to solve the above-described problems, and therefore, has an object to provide a semiconductor device having a better stable operation performance by preventing an element isolating film from being unnecessarily etched away, and by avoiding a failure operation of this semiconductor device caused by unnecessarily removing the element isolating film.
A semiconductor device, according to an aspect of the present invention, comprises: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on said element forming region and extended over said element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under said gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near said gate electrode on said second impurity region; wherein a distance defined from an outer edge of the gate electrode on the side of the first impurity region to another outer edge of said first insulating film on the side apart from said gate electrode is longer than a distance defined from an outer edge of said gate electrode on the side of said second impurity region to another outer edge of said second insulating film on the side apart from said gate electrode.
In this semiconductor device, it is featured that said first and second insulating films are formed from a single insulating film formed on said element forming region and the gate electrode.
Also, said semiconductor device further comprises: an alignment mark, or an overlapping checking mark formed on a desired region of said element isolating film; and an insulating film for covering one of said alignment mark and said overlapping checking mark; wherein both said first insulating film, and said insulating film for covering one of said alignment mark and said overlapping checking mark are formed from a single insulating film formed on one of said alignment mark and said overlapping checking mark, said element forming region, and said gate electrode.
Then, said semiconductor device further comprises: a fuse formed on said element isolating film; and an insulating film formed under said fuse; wherein both said first insulating film and said insulating film formed under said fuse are formed from a single insulating film formed on said element forming region, said gate electrode, and said element isolating film.
Also, a semiconductor device, according to another aspect of the present invention, is featured by comprising: first and second element forming regions formed on one major surface of a semiconductor substrate; an element isolating film formed on said major surface, for electrically isolating said first element forming region from said second element forming region; a first gate electrode formed via a gate insulating film on said first element forming region; a side wall formed on side surfaces of said first gate electrode and said gate insulating film; two sets of first conductivity type of impurity regions having low concentration, formed in said first element forming region and located opposite to each other under said first gate electrode; two sets of first conductivity type impurity regions having high concentration, formed in said first element forming region, whose portions exposed from a surface of said semiconductor substrate are formed outside said two sets of first conductivity type impurity regions having the low-concentration with respect to said gate electrode; a second gate electrode formed via a gate insulating film on said second element forming region; two sets of second conductivity type impurity regions formed in said second element forming region and located opposite to each other under said second gate electrode; and an insulating film formed on said second element forming region and said second gate electrode, and extended over said element isolating film.
A semiconductor device manufacturing method, according to another aspect of the present invention, is featured by comprising the steps of: forming a gate electrode on a plurality of element forming regions formed on one major surface of a semiconductor substrate; forming a first resist mask opened in a desirable element forming region among said plurality of element forming regions; forming a first conductivity type impurity region having low concentration in said desirable element forming region by way of an ion implantation with employment of said gate electrode and said first resist mask; removing said first resist mask to thereby form a second resist mask opened in another desirable element forming region among said plurality of element forming regions; forming a second conductivity type impurity region having high concentration in said another element forming region by way of an ion implantation with employment of said gate electrode and said second resist mask; removing said resist mask to thereby form an insulating film on a plurality of formed element forming regions of said impurity regions; forming a third resist mask opened in said insulating film on the element forming region into which said first conductivity type impurity region having the low concentration is formed; forming a side wall in a side surface of said gate electrode by way of an anisotropic etching process with employment of said third resist mask; and forming a first conductivity type impurity region having high concentration in the element forming region where said first conductivity type impurity region having the low concentration is formed by way of an ion implantation with using said gate electrode, said side wall, and said resist mask.
Also, a semiconductor device manufacturing method, according to another aspect of the present invention, is featured by comprising the steps of: forming gate electrodes on an element forming region formed in one major surface of a semiconductor substrate in such a manner that said gate electrodes are extended over an element isolating film for surrounding said element forming region; forming a pair of impurity regions in said element forming region by way of an ion implantation by using said gate electrodes as a mask; forming an insulating film on said element forming region; forming a resist pattern on said insulating film in such a manner that the resist pattern covers a portion near one of said gate electrodes within said paired impurity regions, said gate electrodes, and a portion near an extended portion of said gate electrode within said element isolating film; and using said resist pattern as a mask to execute an anisotropic etching process of said insulating film.
Also, in the semiconductor device manufacturing method, it is featured by that: in the step for forming the gate electrodes, an alignment mark, or an overlapping checking mark is formed on a desirable region of the element isolating film; in the step for forming the insulating film, an insulating film is formed on one of said alignment mark and said overlapping checking mark; and in the step for forming the resist pattern, another resist pattern is formed which covers one of said alignment mark and said overlapping checking mark.
Further, in the semiconductor device manufacturing method, it is featured by further comprising the step of: forming a fuse on an element isolating film; wherein in the step for forming the insulating film, another insulating film is formed on such a region where said fuse is formed on an upper layer; and in the step for forming the resist pattern, another resist pattern is formed which covers such a region where said fuse is formed on an upper layer.